Day 1

Monday October 26th

13:45 – 14:00

Conference Opening

14:00 – 15:00

Session 1A. Design Methods & Tools (I)

“A block-based systolic array on an HBM FPGA for DNA sequence alignment”, Riadh Ben Abdelhamid and Yoshiki Yamaguchi

Session 1B. Architectures (I)

“Comparison of direct and indirect networks for high-performance FPGA clusters”, Antoniette Mondigo, Tomohiro Ueno, Kentaro Sano and Hiroyuki Takizawa

“Hardware/Algorithm Co-optimization for Fully-Parallelized Compact Decision Tree Ensembles on FPGAs”, Taiga Ikeda, Kento Sakurada, Atsuyoshi Nakamura, Masato Motomura and Shinya Takamaeda-Yamazaki

15:00 – 15:30


15:30 – 16:15


Towards Ubiquitous Accelerators

Mikel Luján
(visit Keynotes)

16:15 – 16:30


16:30 – 17:30

Session 2. Design Methods & Tools (II)

“Improving Performance Estimation for FPGA-based Accelerators for Convolutional Neural Networks, Martin Ferianc, Hongxiang Fan, Ringo S. W. Chu, Jakub Stano and Wayne Luk

“Optimising Operator Sets for Analytical Database Processing on FPGAs”, Anna Drewes, Jan Moritz Joseph, Balasubramanian Gurumurthy, David Broneske, Gunter Saake and Thilo Pionteck

“Automated Toolchain for Enhanced Productivity in Reconfigurable Multi-Accelerator Systems”, Rafael Zamacola, Alberto Ortiz, Alfonso Rodriguez, Andrés Otero and Eduardo de La Torre

17:30 – 17:45


17:45 – 18:45

Session 3. Design Space Exploration & Estimation Techniques

“RISC-V based MPSoC design exploration for FPGAs: Area, Power and Performance”, Muhammad Ali, Pedram Amini Rad and Diana Göhringer

“Accelerating a Classic 3D Video Game on Heterogeneous Reconfigurable MPSoCs, Leonardo Suriano, David Lima and Eduardo de la Torre

“Resource Efficient Dynamic Voltage and Frequency Scaling on Xilinx FPGAs”, Gökhan Akgün, Lester Kalms and Diana Göhringer

18:45 – 19:00


19:00 – 19:45

Session 4. Design Methods & Tools (III)

Judiciously Spreading Approximation among Arithmetic Components with Top-Down Inexact Hardware Design”, Giovanni Ansaloni, Ilaria Scarabottolo and Laura Pozzi

Soft-Error Analysis of Self-Reconfiguration Controllers for Safety Critical Dynamically Reconfigurable FPGAs”, Ludovica Bozzoli and Luca Sterpone

Day 2

Tuesday October 27th

14:00 – 14:40

Session 5. Applications, High-Level Synthesis (I)

FPGA-Based Computational Fluid Dynamics Simulation Architecture via High-Level Synthesis Design Method”, Changdao Du, Iman Firmansyah and Yoshiki Yamaguchi

“Implementation of FM-Index Based Pattern Search on a Multi-FPGA System”, M. M. Imdad Ullah, Akram Ben Ahmed and Hideharu Amano

14:40 – 15:30


15:30 – 16:10

Session 6A. Applications, High-Level Synthesis (II)

StocNoC: Accelerating Stochastic Models through Reconfigurable Network on Chip Architectures”, Arshyn Zhanbolatov, Kizheppatt Vipin, Aresh Dadlani and Dmitriy Fedorov

Session 6B. Architectures (II)

“A Parameterisable FPGA-tailored Architecture for YOLOv3-tiny», Zhewen Yu and Christos-Savvas Bouganis

16:10 – 16:30


16:30 – 17:30

Session 7. Design Space Exploration & Estimation Techniques (II)

“Accuracy, Training Time and Hardware Efficiency Trade-Offs for Quantised Neural Networks on FPGAs”, Pascal Bacchus, Robert Stewart and Ekaterina Komendantskaya

“Cross-Layer CNN Approximations for Hardware Implementation”, Karim M. A. Ali, Ihsen Alouani, Abdessamad Ait El Cadi, Hamza Ouarnoughi and Smail Niar

A CGRA Definition Framework for Dataflow Applications”, George Charitopoulos and Dionisios Pnevmatikatos

17:30 – 17:45

Conference Closure


Virtual Poster Session


All works accepted as poster presentation will be presented offline. Authors will record a pitch of 10 minutes duration. The videos will be uploaded to this site along with author contact information.

(Click on the paper title to see the video or you can see all here)






A Modular Software Library for Effective High-Level Synthesis of Convolutional Neural Networks, Hector Gerardo Muñoz Hernandez, Safdar Mahmood, Marcelo Brandalero and Michael Hübner

HLS-based Acceleration Framework for Deep Convolutional Neural Networks, Ashish Misra and Volodymyr Kindratenko

Implementing CNNs using Linear Array of Full Mesh CGRAs, Valter Mario, Joao Lopes, Mario Vestias and Jose Sousa

“A Vendor and Device Agnostic Technique for Hardware Area-Time Estimation, Deshya Wijesundera, Kushagra Shah, Kisaru Liyanage, Alok Prakash, Thambipillai Srikanthan and Thilina Perera

Chisel Use case: Designing General Matrix Multiply for FPGA, Bruno Ferres, Olivier Muller and Frédéric Rousseau

Cycle-accurate Debugging of Embedded Designs using Recurrent Neural Networks Habib Khan, Ariel Podlubne, Gökhan Akgün and Diana Göhringer

SysIDLib: A High-Level Synthesis FPGA Library for Online System Identification, Gökhan Akgün, Habib ul Hasan Khan, Marawan Hebaish, Mahmoud Elshimy, Mohamed A. Abd El Ghany and Diana Göhringer

Reconfigurable Accelerator for On-Board SAR Imaging Using Back projection, Rui Policarpo Duarte, Helena Cruz and Horacio Neto

High Level Synthesis in Implementing and Benchmarking Number Theoretic Transform in Lattice-based Post-Quantum Cryptography using Software/Hardware Codesign, Duc Tri Nguyen, Viet B. Dang and Kris Gaj

Exploring FPGA optimizations to compute sparse Numerical Linear Algebra kernels”, Federico Favaro, Ernesto Dufrechou, Pablo Ezzatti and Juan P. Oliver

Optimal and Greedy Heuristic Approaches for Scheduling and Mapping of Hardware Tasks to Reconfigurable Computing Devices, Zakarya Guettatfi, Paul Kaufmann and Marco Platzner



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