arc2020_program2020-02-27T16:25:55+00:00

Day 1

Wednesday April 1st

9:00 – 9:30

Registration & Welcome 

9:30 – 10:00

Conference Opening

10:00 – 11:00

Keynote 1

TBA

Keynotes

11:00 – 11:30

Coffee Break

11:30 – 13:00

Session 1. Design Methods & Tools (I)

Chair: TBA

“Improving Performance Estimation for FPGA-based Accelerators for Convolutional Neural Networks, Martin Ferianc, Hongxiang Fan, Ringo S. W. Chu, Jakub Stano and Wayne Luk

“Optimising Operator Sets for Analytical Database Processing on FPGAs”, Anna Drewes, Jan Moritz Joseph, Balasubramanian Gurumurthy, David Broneske, Gunter Saake and Thilo Pionteck

“Automated Toolchain for Enhanced Productivity in Reconfigurable Multi-Accelerator Systems”, Rafael Zamacola, Alberto Ortiz, Alfonso Rodriguez, Andrés Otero and Eduardo de La Torre

13:00 – 14:30

Lunch

14:30 – 16:00

Session 2. Design Space Exploration & Estimation Techniques

Chair: TBA

“RISC-V based MPSoC design exploration for FPGAs: Area, Power and Performance”, Muhammad Ali, Pedram Amini Rad and Diana Göhringer

“Accelerating a Classic 3D Video Game on Heterogeneous Reconfigurable MPSoCs, Leonardo Suriano, David Lima and Eduardo de la Torre

“Resource Efficient Dynamic Voltage and Frequency Scaling on Xilinx FPGAs”, Gökhan Akgün, Lester Kalms and Diana Göhringer

16:00 – 16:15

Poster Pitch 1

Chisel Use case: Designing General Matrix Multiply for FPGA, Bruno Ferres, Olivier Muller and Frédéric Rousseau

Cycle-accurate Debugging of Embedded Designs using Recurrent Neural Networks Habib Khan, Ariel Podlubne, Gökhan Akgün and Diana Göhringer

SysIDLib: A High-Level Synthesis FPGA Library for Online System Identification, Gökhan Akgün, Habib ul Hasan Khan, Marawan Hebaish, Mahmoud Elshimy, Mohamed A. Abd El Ghany and Diana Göhringer

16:15 – 16:45

Coffee Break & Poster Presentation

16:45 – 17:45

Session 3. Architectures (I)

Chair: TBA

A CGRA Definition Framework for Dataflow Applications”, George Charitopoulos and Dionisios Pnevmatikatos

“A block-based systolic array on an HBM FPGA for DNA sequence alignment”, Riadh Ben Abdelhamid and Yoshiki Yamaguchi

20:00

Welcome Cocktail

Day 2

Thursday April 2nd

9:00 – 10:00

Keynote 2

TBA

Keynotes

10:00 – 11:00

Session 4. Design Methods & Tools (II)

Chair: TBA

Judiciously Spreading Approximation among Arithmetic Components with Top-Down Inexact Hardware Design”, Giovanni Ansaloni, Ilaria Scarabottolo and Laura Pozzi

Soft-Error Analysis of Self-Reconfiguration Controllers for Safety Critical Dynamically Reconfigurable FPGAs”, Ludovica Bozzoli and Luca Sterpone

11:00 – 11:30

Coffee Break

11:30 – 13:00

Technical Presentation & Demo

«Xilinx: What’s next in the reprogrammable Era»

Ricardo Gómez

AVNET Silica

13:00 – 14:30

Lunch

14:30 – 16:00

Session 5. Architectures (II)

Chair: TBA

“Comparison of direct and indirect networks for high-performance FPGA clusters”, Antoniette Mondigo, Tomohiro Ueno, Kentaro Sano and Hiroyuki Takizawa

“A Parameterisable FPGA-tailored Architecture for YOLOv3-tiny», Zhewen Yu and Christos-Savvas Bouganis

“Hardware/Algorithm Co-optimization for Fully-Parallelized Compact Decision Tree Ensembles on FPGAs”, Taiga Ikeda, Kento Sakurada, Atsuyoshi Nakamura, Masato Motomura and Shinya Takamaeda-Yamazaki

16:00 – 16:20

Poster Pitch 2

A Modular Software Library for Effective High-Level Synthesis of Convolutional Neural Networks, Hector Gerardo Muñoz Hernandez, Safdar Mahmood, Marcelo Brandalero and Michael Hübner

HLS-based Acceleration Framework for Deep Convolutional Neural Networks, Ashish Misra and Volodymyr Kindratenko

High Level Synthesis in Implementing and Benchmarking Number Theoretic Transform in Lattice-based Post-Quantum Cryptography using Software/Hardware Codesign, Duc Tri Nguyen, Viet B. Dang and Kris Gaj

“Exploring FPGA optimizations to compute sparse Numerical Linear Algebra kernels”, Federico Favaro, Ernesto Dufrechou, Pablo Ezzatti and Juan P. Oliver

16:20 – 17:00

Coffee Break & Poster Presentation

18:00

City Tour & Gala Dinner

Day 3

Friday April 3rd

9:30 – 11:00

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Session 6. Applications, High-Level Synthesis

Chair: TBA

StocNoC: Accelerating Stochastic Models through Reconfigurable Network on Chip Architectures”, Arshyn Zhanbolatov, Kizheppatt Vipin, Aresh Dadlani and Dmitriy Fedorov

FPGA-Based Computational Fluid Dynamics Simulation Architecture via High-Level Synthesis Design Method”, Changdao Du, Iman Firmansyah and Yoshiki Yamaguchi

“Implementation of FM-Index Based Pattern Search on a Multi-FPGA System”, M. M. Imdad Ullah, Akram Ben Ahmed and Hideharu Amano

11:00 – 11:15

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Poster Pitch 3

Optimal and Greedy Heuristic Approaches for Scheduling and Mapping of Hardware Tasks to Reconfigurable Computing Devices, Zakarya Guettatfi, Paul Kaufmann and Marco Platzner

“A Vendor and Device Agnostic Technique for Hardware Area-Time Estimation, Deshya Wijesundera, Kushagra Shah, Kisaru Liyanage, Alok Prakash, Thambipillai Srikanthan and Thilina Perera

“Reconfigurable Accelerator for On-Board SAR Imaging Using Back projection, Rui Policarpo Duarte, Helena Cruz and Horacio Neto

11:15 – 11:45

Coffee Break & Poster Presentation

11:45 – 12:45

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Session 7. Design Space Exploration & Estimation Techniques (II)

Chair: TBA

“Accuracy, Training Time and Hardware Efficiency Trade-Offs for Quantised Neural Networks on FPGAs”, Pascal Bacchus, Robert Stewart and Ekaterina Komendantskaya

“Cross-Layer CNN Approximations for Hardware Implementation”, Karim M. A. Ali, Ihsen Alouani, Abdessamad Ait El Cadi, Hamza Ouarnoughi and Smail Niar

12:45 – 13:15

Conference Closure

13:30 – 15:00

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Lunch

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