T2C-BELIEF SoC RISC-V de alto rendimiento y adaptable

This is a description and registry of results of the proyect T2C-Belief project.

T2C-BELIEF (PDC2023-145865-C32) is a continuation of BELIEF project (PID2020-116417RB-C44)

The overall objective of subproject T2C-BELIEF was to capitalize on the knowledge and results
previously acquired in the domain of adaptive reconfigurable architectures for HSI processing,
with the aim of designing and validating through extensive RTL simulations a heterogeneous
SoC that integrates a soft RISC-V core and custom hardware accelerators deployed in a
reconfigurable fabric. In this way, TALENT-BELIEF outcomes are valorized and getting ready
for industrial use with potential in many areas such as medical imaging, food quality control
and remote sensing, the target use case for this proof-of-concept. The necessary steps will be
taken to convert the already available HSI accelerator technology for standalone FPGA
applications into RISC-V extensions that users could incorporate in their solutions. The
particular objectives of T2C-BELIEF are the following:
O2.1 Evolve TALENT’s library of hyperspectral algorithms into RISC-V compatible operators
optimized for compression, anomaly detection, and feature identification in HSI.
The first goal to achieve is to spot the subset of the most common operators used to handle
HSI data out of the modular and parameterizable description of the algorithms that were
implemented during TALENT-BELIEF. This is necessary to ensure the industry soundness of
the processing platform, being meaningful in real-life applications such as security and
environmental monitoring using hyperspectral data gathered from earth observation platforms.
KPI 2.1.1: Identify at least 5 operators for HSI processing.
KPI 2.1.2: RTL models of RISC-V compatible accelerators that support the new HSI
operators and at least 3 optimized variants of each to ensure application specific
customization.
KPI 2.1.3: Implement at least 3 HSI processing algorithms to validate the RTL
accelerators through cycle-accurate co-simulation.
O2.2 Development of a heterogeneous RISC-V based System-on-Chip architecture for high-
performance, low power remote sensing applications.
When it comes to architectural alternatives to actually integrate hardware accelerators into the
base RISC-V datapath, two main strategies are available to hardware engineers. On the one
hand, the tightly coupled style usually makes use of a command/response module that receives custom processor instructions following the RISC-V R type instruction format. On the
other hand, the loosely coupled way, the RISC-V core supports a standardized interface such
as the Tilelink or any other shared-memory approach. This objective aims to explore the
technical viability of using each alternative so the best solution for HSI processing is selected.
● KPI 2.2.1: 1 RTL specification of a RISC-V SoC architecture with tightly-coupled FPGA
HSI accelerators.
● KPI 2.2.2: 1 RTL specification of a RISC-V SoC architecture with loosely-coupled FPGA
HSI accelerators.
● KPI 2.2.3: Benchmarking and validation of the two architectural approaches explored
via exhaustive simulation of the execution of 3 HSI processing algorithms.

O2.3 Integrate TALENT’s reconfiguration techniques and tools for FPGA’s based context-
aware algorithms into the HSI processing platform.

Reconfigurable architectures enable the adaptability of the architecture on unexpected events
or changes in the execution scenery. These are desirable features for remote sensing
platforms that can dynamically adapt the applications to reductions in the energy budget or to
provide extra computing power in order to get higher accuracy in the results. This objective
pursuit the applicability of previous developments in TALENT in the field of dynamic
reconfigurable SoC architectures based on RISC-V standard.
●KPI 2.3.1: Provide at least 2 versions of the RTL HSI accelerators for low-power and
high-performance execution scenarios.
●KPI 2.3.2: Provide the RISC-V heterogeneous SoC with runtime reconfiguration
capabilities that change the accelerator implementation in the dynamic region in less
than a second.

Proyecto PDC2023-145865-C32 , financiado por MICIU/AEI/10.13039/501100011033 y por la Unión Europea «NextGeneration EU»/PRTR»