Testing framework for in-hardware verification of the hardware modules generated using HLS

Computer Architecture and Networks Group, University of Castilla-La Mancha, Ciudad Real, Spain

Julian.Caba@uclm.es

Computer Architecture and Networks Group, University of Castilla-La Mancha, Ciudad Real, Spain

Fernando.Rincon@uclm.es

Computer Architecture and Networks Group, University of Castilla-La Mancha, Ciudad Real, Spain

Julio.Dondo@uclm.es

Computer Architecture and Networks Group, University of Castilla-La Mancha, Ciudad Real, Spain

Jesus.Barba@uclm.es

Computer Architecture and Networks Group, University of Castilla-La Mancha, Ciudad Real, Spain

ManuelJose.Abaldea@uclm.es

Computer Architecture and Networks Group, University of Castilla-La Mancha, Ciudad Real, Spain

JuanCarlos.Lopez@uclm.es

  • CONFERENCE — International Workshop on Power and Timing Modeling, Optimization and Simulation

  • PAGES — 103-110

  • ISBN — 978-1-5386-6365-3

  • DATE 02/07/2018 – 04/07/2018

  • LOCATION Costa Brava (Girona, España)

  • YEAR  2018

Caba, J., Rincón, F., Dondo, J., Barba, J., Abaldea, M., & López, J. C. (2018, July). Testing Framework for in-Hardware Verification of the Hardware Modules Generated Using HLS. In 2018 28th International Symposium on Power and Timing Modeling, Optimization and Simulation (PATMOS) (pp. 103-110). IEEE.

@inproceedings{caba2018testing,
title={Testing Framework for in-Hardware Verification of the Hardware Modules Generated Using HLS},
author={Caba, Juli{\'a}n and Rinc{\'o}n, Fernando and Dondo, Julio and Barba, Jes{\'u}s and Abaldea, Manuel and L{\'o}pez, Juan Carlos},
booktitle={2018 28th International Symposium on Power and Timing Modeling, Optimization and Simulation (PATMOS)},
pages={103--110},
year={2018},
organization={IEEE}
}

Abstract

High-Level Synthesis (HLS) allows Field Programmable Gate Array (FPGA) developers to easily implement complex applications in silicon, addressing the ever-growing size and complexity of modern embedded reconfigurable systems. Unfortunately, in spite of these advancements, new non-negligible verification problems arise. For instance, the co-simulation strategy may not provide trustworthy results due to the variable accuracy of simulation, or hardware synthesis issues (e.g. those related to signal routing) which are not detectable in the simulation. Hence, developers need new verification mechanisms to reduce the gap between the technology and the verification needs. In this paper, we propose a testing framework and a hardware verification platform based on FPGA technology in order to improve the verification accuracy and enable effortless and fully automatic in-hardware system validation. For instance, one of the mechanisms is the inclusion of physical configuration macros (e.g., clock rate configuration macro) and test assertions based on physical parameters in the verification environment (e.g., timing assertions). Experiment results demonstrate our approach in the context of a case study remaining the same testing technology independently of the module abstraction level.

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