Rapid Prototyping and Verification of Hardware Modules Generated Using HLS

Computer Architecture and Networks Group, University of Castilla-La Mancha, Ciudad Real, Spain

Julian.Caba@uclm.es

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Computer Architecture and Networks Group, University of Castilla-La Mancha, Ciudad Real, Spain

Fernando.Rincon@uclm.es

Computer Architecture and Networks Group, University of Castilla-La Mancha, Ciudad Real, Spain

Ruben.Cantarero@uclm.es

Computer Architecture and Networks Group, University of Castilla-La Mancha, Ciudad Real, Spain

Julio.Dondo@uclm.es

Computer Architecture and Networks Group, University of Castilla-La Mancha, Ciudad Real, Spain

JuanCarlos.Lopez@uclm.es

  • CONFERENCE — International Workshop on Applied Reconfigurable Comuting

  • PAGES — 446-458

  • ISBN — 978-3-319-78889-0

  • DATE  02/05/2018 – 04/05/2018

  • PUBLISHER  Springer

  • YEAR  2018

  • LOCATION  Santorini (Grecia)

Caba, J., Cardoso, J. M., Rincón, F., Dondo, J., & López, J. C. (2018). Rapid Prototyping and Verification of Hardware Modules Generated Using HLS. In Applied Reconfigurable Computing. Architectures, Tools, and Applications: 14th International Symposium, ARC 2018, Santorini, Greece, May 2-4, 2018, Proceedings 14 (pp. 446-458). Springer International Publishing.

@inproceedings{caba2018rapid,
title={Rapid Prototyping and Verification of Hardware Modules Generated Using HLS},
author={Caba, Juli{\'a}n and Cardoso, Jo{\~a}o MP and Rinc{\'o}n, Fernando and Dondo, Julio and L{\'o}pez, Juan Carlos},
booktitle={Applied Reconfigurable Computing. Architectures, Tools, and Applications: 14th International Symposium, ARC 2018, Santorini, Greece, May 2-4, 2018, Proceedings 14},
pages={446--458},
year={2018},
organization={Springer International Publishing}
}

Abstract

Most modern design suites include HLS tools that rise the design abstraction level and provide a fast and direct flow to programmable devices, getting rid of manually coding at the RTL. While HLS greatly reduces the design productivity gap, non-negligible problems arise. For instance, the co-simulation strategy may not provide trustworthy results due to the variable accuracy of simulation, especially when considering dynamic reconfiguration and access to system busses. This work proposes mechanisms aimed at improving the verification accuracy using a real device and a testing framework. One of the mechanisms is the inclusion of physical configuration macros (e.g., clock rate configuration macro) and test assertions based on physical parameters in the verification environment (e.g., timing assertions). In addition it is possible to change some of those parameters, such as clock speed rate, and check the behavior of a hardware component into an overclocking or underclocking scenario. Our on-board testing flow allows faster FPGA iterations to ensure the design intent and the hardware-design behavior match. This flow uses a real device to carry out the verification process and synthesizes only the DUT generating its partial bitstream in a few minutes.

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2019-01-17T14:24:48+00:00