Functional & timing in-hardware verification of FPGA-based designs using unit testing frameworks
Computer Architecture and Networks Group, University of Castilla-La Mancha, Ciudad Real, Spain
Julian.Caba@uclm.es
Computer Architecture and Networks Group, University of Castilla-La Mancha, Ciudad Real, Spain
Julio.Dondo@uclm.es
Computer Architecture and Networks Group, University of Castilla-La Mancha, Ciudad Real, Spain
Fernando.Rincon@uclm.es
CONFERENCE — International Conference on Field Programmable Logic and Applications
ISBN — 978-9-0903-0428-1
DOI — 10.23919/FPL.2017.8056849
PUBLISHER — IEEE
YEAR — 2017
LOCATION — Ghent, Belgium
@inproceedings{caba2017functional,
title={Functional \& timing in-hardware verification of FPGA-based designs using unit testing frameworks},
author={Caba, Julian and Rincoon, Fernando and Dondo, Julio Daniel},
booktitle={Field Programmable Logic and Applications (FPL), 2017 27th International Conference on},
pages={1--2},
year={2017},
organization={IEEE}
}
Abstract
In this PhD dissertation, we propose a new testing approach for effectively managing hardware development risks, producing hardware designs with enough quality and reliability. Our proposal is based on the combination of high-level modelling and a unit testing framework in order to generate real hardware implementations for validating the designer intent, in order to keep a high cycle-accuracy and a low design effort. Such real hardware implementations are based on FPGAs, whose reconfigurability are key to provide a flexible verification environment, whereas unit testing frameworks have been extended to consider new testing requirements beyond pure functionality, such as timing analysis. Moreover, we provide a hardware library with two different types of components: 1) monitors to check internal variables at run time, keeping the errors to later trace them, and 2) double functions to reduce third-party dependencies.
