Building a Dynamically Reconfigurable System Through a High Development Flow

Computer Architecture and Networks Group, University of Castilla-La Mancha, Ciudad Real, Spain

Computer Architecture and Networks Group, University of Castilla-La Mancha, Ciudad Real, Spain

Jesus.Barba@uclm.es

No disponemos de la información de contacto de este autor.

Computer Architecture and Networks Group, University of Castilla-La Mancha, Ciudad Real, Spain

JuanCarlos.Lopez@uclm.es

No disponemos de la información de contacto de este autor.

No disponemos de la información de contacto de este autor.

  • CONFERENCE — International Forum on Design Languages

  • PAGES — 1-8

  • ISBN — 978-1-4673-7735-5

  • PUBLISHER  IEEE

  • YEAR  2015

  • LOCATION  Barcelona, Spain

De La Fuente, D., Barba, J., Pena, X., Lopez, J. C., Penil, P., & Sanchez, P. P. (2015, September). Building a dynamically reconfigurable system through a high development flow. In Specification and Design Languages (FDL), 2015 Forum on (pp. 1-8). IEEE.

@inproceedings{de2015building,
title={Building a dynamically reconfigurable system through a high development flow},
author={De La Fuente, David and Barba, Jesus and Pena, Xerach and Lopez, Juan Carlos and Penil, Pablo and Sanchez, Pablo Pedro},
booktitle={Specification and Design Languages (FDL), 2015 Forum on},
pages={1--8},
year={2015},
organization={IEEE}
}

Abstract

Partial Reconfiguration is one of the most attractive features of FPGAs. This feature provides new computing possibilities, such as the reduction of the total area required in a FPGA by means of functioning overlapping, or the modification of the design after its deployment, where a complete configuration is not needed. However, the design of partially reconfigurable systems is still a complex task. This work focuses on facilitating the design process and proposes a new development framework for dynamically configurable systems from high level UML/MARTE models which, starting from dynamically reconfigurable systems high level UML/MARTE models. Simulation and VHDL code are generated from those models, according to the specification requirements of the reconfigurable hardware captured in the specifications.

DOWNLOAD PDF
PUBLICATION

OTRAS PUBLICACIONES

Load More Posts
2019-01-24T13:21:30+00:00