Integrating reconfigurable hardware-based grid for high performance computing

Computer Architecture and Networks Group, University of Castilla-La Mancha, Ciudad Real, Spain

Julio.Dondo@uclm.es

Computer Architecture and Networks Group, University of Castilla-La Mancha, Ciudad Real, Spain

Fernando.Rincon@uclm.es

Computer Architecture and Networks Group, University of Castilla-La Mancha, Ciudad Real, Spain

JuanCarlos.Lopez@uclm.es

  • JOURNAL — Scientific World Journal

  • PAGES — 1-19

  • ISSN — 1537-744X (Online)

  • VOLUME 60

  • PUBLISHER HINDAWI

  • YEAR  2014

Dondo Gazzano, J., Sanchez Molina, F., Rincon, F., & López, J. C. (2015). Integrating reconfigurable hardware-based grid for high performance computing. The Scientific World Journal2015.

@article{dondo2015integrating,
title={Integrating reconfigurable hardware-based grid for high performance computing},
author={Dondo Gazzano, Julio and Sanchez Molina, Francisco and Rincon, Fernando and L{\'o}pez, Juan Carlos},
journal={The Scientific World Journal},
volume={2015},
year={2015},
publisher={Hindawi}
}

Abstract

FPGAs have shown several characteristics that makes them very attractive for high performance computing (HPC). The impressive speed-up factors that they are able to achieve, a reduced power consumption, and the easiness and flexibility of the design process with fast iterations between consecutive versions are examples of benefits obtained with their use. However, there are still some difficulties when using reconfigurable platforms as accelerator that need to be addressed: the need of an in-depth application study to identify potential acceleration, the lack of tools for the deployment of computational problems in distributed hardware platforms, and the low portability of components, among others. This work proposes a complete grid infrastructure for distributed high-performance computing based on dynamically reconfigurable FPGAs. Besides, a set of services designed to facilitate the application deployment is described. An example application and a comparison with other hardware and software implementations are shown. Experimental results show that the proposed architecture offers encouraging advantages for deployment of high performance distributed applications simplifying development process.

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